FPGA中的多時(shí)鐘域設(shè)計(jì)

覺(jué)得這篇文章很好，因此在這里翻譯一下——或者也可以說(shuō)是按我的理解加中文注釋。

MulTIple, independent clocks are ubiquitous in system-on-chip (SoC) design. Most SoC devices have mulTIple interfaces, some following standards that use very different clock frequencies.
在一個(gè)SOC設(shè)計(jì)中，存在多個(gè)、獨(dú)立的時(shí)鐘，這已經(jīng)是一件很平常的事情了。大多數(shù)的SOC器件都具有很多個(gè)接口，各個(gè)接口標(biāo)準(zhǔn)都可能會(huì)使用完全不同的時(shí)鐘頻率。

Many modern serial interfaces are inherently asynchronous from the rest of the chip; some actually derive their clocks directly from the incoming data streams. There is also a trend toward designing major sub-blocks of SoCs to run on independent clocks to ease the problem of clock skew across large chips.
例如對(duì)于現(xiàn)代的串行通信接口而言，它們自然而然地就與芯片的其余部分是不同步的，因?yàn)樗鼈兊臅r(shí)鐘有時(shí)候就是直接從數(shù)據(jù)流中恢復(fù)出來(lái)的。而且，現(xiàn)在還有一個(gè)趨勢(shì)，就是有時(shí)候?yàn)榱嗽诒苊獯笮酒辛钊祟^痛的所謂clocl skew問(wèn)題，索性讓各個(gè)子模塊都具有獨(dú)立的時(shí)鐘。

For all of these reasons, designers working on SoC projects are virtually certain to encounter mulTIple clocks and to be faced with the design of logic interconnecTIng two portions of the chip running on independent clocks. Each such portion is known as a clock domain. The interface between logic on different clocks is called a clock domain crossing or clock domain boundary. The proper handing of signals across clock domain boundaries is critical for successful SoC design.
因?yàn)橐陨显?，進(jìn)行SOC設(shè)計(jì)時(shí)，常常要考慮工作在不同時(shí)鐘下的兩個(gè)部分邏輯之間的互連問(wèn)題，而每個(gè)部分，都可稱(chēng)之為“時(shí)鐘域”，連接它們之間的那部分?jǐn)?shù)字邏輯可稱(chēng)為“時(shí)鐘邊界”或所謂“跨時(shí)鐘域”。合理地處理跨時(shí)鐘的問(wèn)題，對(duì)于一個(gè)成功的SOC設(shè)計(jì)來(lái)說(shuō)非常關(guān)鍵。

Problem #1: Meta-stability

The first multi-clock problem that designers must consider is that of meta-stability as signals pass from one clock domain to another. Most designers understand that meta-stability is a real problem in real circuits; the modern abstractions of RTL design and static timing analysis cant entirely shield designers from having to worry about the underlying physics.
1) 亞穩(wěn)態(tài)
多時(shí)鐘域設(shè)計(jì)的第一個(gè)問(wèn)題，便是信號(hào)從一個(gè)時(shí)鐘域傳輸?shù)搅硪粋€(gè)時(shí)鐘域的時(shí)候，可能會(huì)出現(xiàn)亞穩(wěn)態(tài)。 許多設(shè)計(jì)者都知道，在真實(shí)的電路中的確會(huì)存在所謂亞穩(wěn)態(tài)的問(wèn)題。但是，在現(xiàn)代的FPGA設(shè)計(jì)中，即使設(shè)計(jì)者面對(duì)的是RTL級(jí)抽象和靜態(tài)時(shí)序分析，卻仍然不能完全將這個(gè)問(wèn)題拒之門(mén)外，因?yàn)槌橄蟮难谏w之下，我們?nèi)匀槐苊獠涣苏鎸?shí)的物理規(guī)律。

Whenever a signal enters a clocked circuit element, such as a flip-flop, too close to the clock, there is the potential for meta-stability. When this happens, the flip-flop may not immediately settle to a known value. It is critical that the output signal from the flip-flop not be used until it has settled.
任何時(shí)候，一個(gè)信號(hào)輸入到一個(gè)時(shí)鐘觸發(fā)的電路——例如一個(gè)D觸發(fā)器，當(dāng)信號(hào)(跳變)過(guò)于靠近時(shí)鐘前沿，便會(huì)存在所謂亞穩(wěn)態(tài)問(wèn)題。這個(gè)時(shí)候，DFF的輸出端不會(huì)馬上產(chǎn)生一個(gè)可預(yù)知的值，也就是說(shuō)，在這段時(shí)間內(nèi)，輸出信號(hào)是無(wú)效的。

On a truly asynchronous clock boundary, the receiving domains clock is used to capture each signal from the driving domain in a flip-flop. Because there is no defined temporal relationship between the clock and the signal, it is entirely possible that they could transition at the same time. Whenever this happens, there is a possibility of meta-stability in the receiving clock domain.
在設(shè)計(jì)中，常常會(huì)用一個(gè)觸發(fā)器接收來(lái)自于另一個(gè)時(shí)鐘域的輸出信號(hào)(即用本地時(shí)鐘的前沿來(lái)鎖存另一個(gè)時(shí)鐘域的信號(hào)）。由于觸發(fā)器的時(shí)鐘和數(shù)據(jù)輸入信號(hào)不存在確定的相位關(guān)系，因此完全有可能出現(xiàn)數(shù)據(jù)和時(shí)鐘同時(shí)跳變的情況。這樣，就在接收端所在的時(shí)鐘域中造成了亞穩(wěn)態(tài)。

This is not just a theoretical potential. GHz-rate chips with clocking design errors can exhibit the effects of meta-stability quite quickly when running in real systems. These effects typically include loss of critical handshake signals between clocks domains, and corruption of multi-bit dataserious problems that are highly likely to require a chip re-spin.
亞穩(wěn)態(tài)的風(fēng)險(xiǎn)，并不僅僅是理論上的。對(duì)于GHz數(shù)據(jù)率的芯片，如果時(shí)鐘設(shè)計(jì)考慮不當(dāng)，一旦把它放到實(shí)際系統(tǒng)中運(yùn)行，亞穩(wěn)態(tài)的效果所造成的危害很快就會(huì)表現(xiàn)出來(lái)。最典型的比如說(shuō)，跨時(shí)鐘域的關(guān)鍵握手信號(hào)丟失，以及并行數(shù)據(jù)出錯(cuò)。然后這個(gè)芯片的設(shè)計(jì)很可能就泡湯，于是你不得不推倒重來(lái)。(所謂 re-spin，按我的理解，是重新開(kāi)始的意思)

Most designers also know that the textbook solution to meta-stability is using two levels of flip-flops on each signal crossing a clock domain boundary. Even if the first flip-flop does become meta-stable, there is an extremely high likelihood that the signal will settle by the time that it passes through the second level. The double-level flip-flop structure is often called a synchronizer, and designers commonly speak of synchronizing signals across clock domains.
多數(shù)設(shè)計(jì)者都已經(jīng)知道，對(duì)于亞穩(wěn)態(tài)，教科書(shū)上經(jīng)典的解決辦法，就是在凡時(shí)鐘邊界的地方，都用兩級(jí)(D)觸發(fā)器對(duì)信號(hào)進(jìn)行同步。這樣的話，哪怕第一級(jí)D觸發(fā)器進(jìn)入了亞穩(wěn)態(tài)，后一級(jí)也極有可能把它克服掉。這種兩級(jí)觸發(fā)器結(jié)構(gòu)，通常稱(chēng)為“synchronizer”，這個(gè)過(guò)程也稱(chēng)為跨時(shí)鐘域信號(hào)同步。

Problem #2: Reset synchronization 復(fù)位的同步問(wèn)題
Improper synchronization of reset signals is a related problem in multi-clock designs. Designers sometimes forget that reset signals are subject to meta-stability and must be protected by synchronizers. Generally, the entire SoC can be reset by a single signal, which therefore must propagate to all clocked elements in all clock domains.
復(fù)位信號(hào)的不同步，也是一個(gè)與多時(shí)鐘設(shè)計(jì)相關(guān)的問(wèn)題。設(shè)計(jì)者有時(shí)候會(huì)忘了一個(gè)事實(shí)，那就是復(fù)位信號(hào)也可能引起亞穩(wěn)態(tài)問(wèn)題，而且必須用synchronizers來(lái)對(duì)它進(jìn)行同步。通常來(lái)說(shuō)，每個(gè)SOC都會(huì)有一個(gè)reset信號(hào)，這個(gè)信號(hào)被送到各個(gè)時(shí)鐘域的各個(gè)同步邏輯單元，來(lái)對(duì)整個(gè)芯片/系統(tǒng)進(jìn)行復(fù)位。

There is no need for synchronization on the activation edge of reset, since by definition all state elements are reset to initial values, and the reset signal will generally be held active for enough cycles to allow any meta-stability to settle out.