Δ－Σ轉(zhuǎn)換器的信噪比如何不同

　　當(dāng)我還是孩子的時候，父母送給我一個內(nèi)徑為1的箱子。我非常的興奮！為了保護這個海龜，我準備把它放到我的貨車上。車上有個狹槽可以嵌入方形，三角形和圓形的銷子。媽媽看到我拿走一個錘子，就知道肯定不會有好事。她對我說：“你不能將一個方形的銷子放進一個圓形的孔中”。

　　這件教訓(xùn)也同樣適用于下面的Δ－Σ調(diào)節(jié)器和ADC中——一個從1930年起被提出的基本概念。轉(zhuǎn)換器的拓撲結(jié)構(gòu)與其他拓撲的結(jié)構(gòu)有一點不同。然而，許多工程師仍努力使轉(zhuǎn)換器適應(yīng)標準ADC方形孔。

　　Δ－Σ轉(zhuǎn)換器的性能遠超一般簡單的模數(shù)轉(zhuǎn)換器。它有過采樣結(jié)構(gòu)、調(diào)節(jié)器和數(shù)字濾波器。過采樣結(jié)構(gòu)在較寬的頻率范圍內(nèi)擴展噪聲功率。調(diào)節(jié)器形成低頻噪聲或?qū)⑵渫频礁哳l率。數(shù)字濾波器可以平滑噪聲信號并將其從高頻信號中消除。完美的逐次逼近記錄寄存器和傳遞途徑信噪比為6.02N+1.76（參考文獻1），其中N為轉(zhuǎn)換器位數(shù)。Δ－Σ轉(zhuǎn)換器的信噪比是6.02(N+N_INC)+1.76，其中，N是調(diào)節(jié)器位數(shù)，N_INC是增加的分辨率是：

　　在這個公式中，M是調(diào)節(jié)器階數(shù)，K是轉(zhuǎn)換過程中的過采樣速率。

　　理想的帶一階調(diào)節(jié)器的Δ－Σ轉(zhuǎn)換器信噪比是6.02N+1.76–5.17 +30log₁₀OSR，其中OSR為過采樣速率，N為調(diào)制器位數(shù)而不是轉(zhuǎn)換器的位數(shù)（如圖1）。

　　這些理想公式假定ADC和DAC的噪聲和偏移誤差為線性的，通常一階設(shè)備是理想的，數(shù)字濾波器也會有一個理想的磚墻型反應(yīng)。事實上，Δ－Σ轉(zhuǎn)換器并不想我們希望的那么理想。

　　由這些理想的理論，最好的方法仍是依靠轉(zhuǎn)換器性能的基準數(shù)據(jù)。這些數(shù)據(jù)給你轉(zhuǎn)換器性能的現(xiàn)實看法。在這個基礎(chǔ)上，通過獲取上百次直流輸入信號的采樣，來測量轉(zhuǎn)換器的均方根噪聲。在這種情形中，描述任意ADC信噪比的公式是20log₁₀(V_RMS-FS/V_RMS-NOISE)。

　　參考文獻：

　　1．Baker, Bonnie, “Where did all the bits go?” EDN, June 7, 2007, pg 36.

　　2．Baker, RJ, CMOS Mixed-Signal Circuit Design, Wiley-IEEE Press, 2002.

　　3．Norsworthy, Steven R, Richard Schreier, and Gabor C Temes, Delta-Sigma Converters: Theory, Design, and Simulation, Wiley-IEEE Press, 1996.

　　英文原文：

　　How the SNRs of delta-sigma converters differ

　　This converter topology is a bit different from other topologies; however, many engineers still strive to fit this round peg of a converter into the standard ADC square hole.

　　By Bonnie Baker -- EDN, 8/2/2007

　　When I was a child, my parents bought me a 1-in.-diameter box turtle. I was so excited! To protect the turtle, I was going to put it in my block wagon. This wagon had slots to insert square, triangular, and round pegs. When my mom saw me grab a hammer, she knew it wouldn’t be a pretty picture. “You can’t fit a square peg—or a turtle—into a round hole,” she told me.

    That lesson also applies to the basic concept underlying delta-sigma modulators and ADCs—a concept that has been around since the 1930s. This converter topology is a bit different from other topologies; however, many engineers still strive to fit this converter into the standard ADC square hole.

　　Delta-sigma converters go beyond performing a simple analog-to-digital conversion. They have an oversampling mechanism, a modulator, and a digital filter. The oversampling mechanism spreads the noise power across a wider frequency range. The modulator shapes the low-frequency noise or pushes it out to higher frequencies. The digital filter averages the noise and eliminates it in the higher frequencies. The id eal successive-approximation-register and pipeline SNR (signal-to-noise ratio) is 6.02N+1.76 (Reference 1), where N is the number of converter bits. The delta-sigma-converter SNR is 6.02(N+NINC)+1.76, where N is the number of modulator bits and NINC, the increase in resolution, is:

　　In this formula, M is the order of the modulator, and K is the oversampling ratio during the conversion.

　　Ideally, the delta-sigma-converter SNR, with a first order modulator, is 6.02N+1.76–5.17+30log10OSR where OSR is the oversampling rate and N is the number of modulator bits—not converter bits (Figure 1).

　　These ideal formulas assume that the linearity, noise, and offset errors of the ADC and DAC—usually, 1-bit devices—are ideal and that the digital filter has an ideal brick-wall response. Actual delta-sigma converters are not as ideal as you would hope.

　　With these theories of the ideal, the best approach is still to rely on bench data for your converter performance. This data gives you a realistic view of the converter’s capabilities. On the bench, you can measure your converter’s rms noise by acquiring a few hundred samples of a dc-input signal. In this circumstance, the formula that describes any ADC SNR is 20log10(VRMS-FS/VRMS-NOISE).