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均衡器的工作原理與設(shè)計(jì)

積分：0分 keysight SERDES Equalizers CTLE FFE DFE |

EEPW

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SerDes Overview

積分：0分 SerDes Overview |

zhuanjifen

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一個(gè)用于測(cè)量，識(shí)別和消除對(duì)高速串行通信鏈路的時(shí)鐘和數(shù)據(jù)抖動(dòng)的建議框架

積分：0分 Maxim jitter clock jitter data jitter high-speed serial signal integrity SERDES serializer-deserializer clock and data recovery CDR jitter tolerance CPRI common public radio interface bit error rate BER deterministic jitter random jitter |

soothmusic

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內(nèi)置誤碼率測(cè)試電路中使用的2.5Gbps SerDes的測(cè)量鏈路質(zhì)量容易

積分：0分 Maxim high speed interconnect GMSL BER eye diagram pre-emphasis equalization serializer deserializer serdes PRBS |

soothmusic

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在Maxim GMSL SerDes器件中預(yù)加重和均衡

積分：0分 Maxim serializer deserializer SerDes preemphasis equalization STP shielded twisted pair video high speed data cable compensation GMSL gmsl |

soothmusic

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內(nèi)置誤碼率測(cè)試電路中使用的2.5Gbps SerDes的測(cè)量鏈路質(zhì)量容易

積分：0分 Maxim high speed interconnect GMSL BER eye diagram pre-emphasis equalization serializer deserializer serdes PRBS |

soothmusic

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在Maxim GMSL SerDes器件預(yù)加重和均衡

積分：0分 Maxim serializer deserializer SerDes preemphasis equalization STP shielded twisted pair video high speed data cable compensation GMSL gmsl |

soothmusic

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一個(gè)用于測(cè)量，識(shí)別和消除對(duì)高速串行通信鏈路的時(shí)鐘和數(shù)據(jù)抖動(dòng)的建議框架

積分：0分 Maxim jitter clock jitter data jitter high-speed serial signal integrity SERDES serializer-deserializer clock and data recovery CDR jitter tolerance CPRI common public radio interface bit error rate BER deterministic jitter random jitter |

soothmusic

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【用戶(hù)指南】Altera收發(fā)器PHY IP核用戶(hù)指南(Altera Transceiver PHY IP Core User Guide)

積分：0分 Altera transceiver xcvr SERDES TX RX 10GBASE-R XAUI Interlaken PCI Express PIPE custom low latency deterministic latency PHY IP core |

bobgeng

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一個(gè)用于測(cè)量，識(shí)別和消除對(duì)高速串行通信鏈路的時(shí)鐘和數(shù)據(jù)抖動(dòng)的建議框架

積分：0分 Maxim jitter clock jitter data jitter high-speed serial signal integrity SERDES serializer-deserializer clock and data recovery CDR jitter tolerance CPRI common public radio interface bit error rate BER deterministic jitter random jitter |

soothmusic

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一個(gè)用于測(cè)量，識(shí)別和消除對(duì)高速串行通信鏈路的時(shí)鐘和數(shù)據(jù)抖動(dòng)的建議框架

積分：0分 Maxim jitter clock jitter data jitter high-speed serial signal integrity SERDES serializer-deserializer clock and data recovery CDR jitter tolerance CPRI common public radio interface bit error rate BER deterministic jitter random jitter |

soothmusic

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【應(yīng)用手冊(cè)】AN 571: Implementing the SERDES Framer Interface Level 5 (SFI-5.1) Protocol in Stratix IV Devices

積分：0分 Altera FPGA Stratix IV SERDES Framer Interface Level 5 (SFI-5.1) Protocol |

bobgeng

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【應(yīng)用手冊(cè)】AN 572: Implementing the Scalable SERDES Framer Interface (SFI-S) Protocol in Stratix IV GT Devices

積分：0分 Altera FPGA Stratix IV GT Scalable SERDES Framer Interface protocol |

bobgeng

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內(nèi)置誤碼率測(cè)試電路中使用的2.5Gbps SerDes的測(cè)量鏈路質(zhì)量容易